A successive approximation register (SAR) comprises an analog to digital conversion method in which the input voltage is compared with the output voltage of a sequentially programmed digital to analog converter. First, the most significant bit (MSB) of the digital to analog converter is turned on and compared with an analog input voltage. If the input voltage is greater than the digital to analog output, the MSB is left at logic high. Otherwise, the MSB is turned to logic low. This process is repeated for all other bits in decreasing order until the least significant bit (LSB) is reached.
A very popular digital to analog converter architecture used in CMOS technology is the charge scaling DAC. A 10-bit split array binary weighted (binary coded) DAC includes capacitors on both sides of a bridge capacitor that are binary weighted. A capacitance value C is the unit capacitor of any value. This DAC architecture is widely used in charge distribution ADCs. The capacitor array itself is the critical component of the ADC because of the need for precisely/accurately ratioed capacitors. The linearity of the ADC depends on the matching between the ratios of the capacitors associated with the bits of the array. As the number of bits increases, the ratio of the MSB capacitor to the LSB capacitor becomes more difficult to control. The ratio mismatches between the capacitors are greatly reduced by building each capacitor out of the unit capacitor C and by using special layout techniques. Yet there is a great need to further improve the matching of the capacitor ratios, especially with an increase in the number of bits. For ADCs with higher bits (equal to or higher than 10 bits), capacitor calibration techniques are used to achieve better matching between the capacitors. However, this technique would require additional calibration circuits.
Additionally, the comparators used within some types of SAR ADC circuits have large transients applied to their inputs using existing coding techniques. As long as these transients settle down within the time allowed for the comparison by the comparator, this is not a problem. However, for ADCs with higher resolution and speed, the larger transients may place a limitation on the settling times of the input node of the comparator. Thus, there's a need to improve the operation of SAR analog to digital converters within a digital to analog converter with smaller transients for higher resolution comparators and some method for improving the matching between capacitors without requiring any additional calibration circuits.